Name: The Foundation of Iron — Week 3 — Boolean Algebra and Logic Circuits
Author: Amine RAITI

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THE FOUNDATION OF IRON · COURSE MATERIAL · WEEK 3

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BOOLEAN ALGEBRA
AND LOGIC CIRCUITS
Week 3 of 26 · Block 1 — Fundamentals
12h theory · 23h practice

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◆ WEEKLY LEARNING OBJECTIVES

1. Know the basic logic operators (AND, OR, NOT, NAND, NOR, XOR) and their truth tables
2. Simplify a logic function using Boolean algebra
3. Simplify a logic function using a Karnaugh map
4. Design a logic circuit from a specification
5. Build and test a logic circuit using 74XXX-series integrated circuits

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NOTE FOR THE INSTRUCTOR

This week is deliberately practice-heavy (23h out of 35h) — the theory stays short and lends itself to immediate verification on hardware. Keep Exercises 1 and 2 back to back, as the final project directly depends on what they cover.

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Amine RAITI · Infrastructure Architect & SRE
Public document · CC BY-NC-SA 4.0 · AI Powered by Amine
Opération Dindon

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COURSE OUTLINE · 12H

THEORY GUIDING THREAD

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3.1 · Basic logic operators3h

— AND (.), OR (+), NOT (overline) — truth tables to build together
— Derived operators: NAND, NOR, XOR — truth tables
— Key point: NAND and NOR are "universal" operators (any circuit can be built with them alone)

3.2 · Laws of Boolean algebra3h

— Basic laws: commutativity, associativity, distributivity
— De Morgan's laws (very important going forward): NOT(A.B) = NOT(A)+NOT(B)
— Example to work through on the board: simplify A.B + A.NOT(B) = A

3.3 · Karnaugh maps4h

— Building a Karnaugh map for 2, 3, then 4 variables
— Method for grouping adjacent cells (powers of 2)
— Reading the simplified result from the groupings
— Example to work through: simplify a 3-variable function from a given truth table

3.4 · Circuit design methodology2h

— Steps: specification → defining input/output variables → truth table → simplification (Boolean algebra or Karnaugh) → logic diagram → physical build
— Presentation of this week's case study: traffic light control at a simple intersection

EXAMPLE TO DEVELOP ON THE BOARD

Applying De Morgan's law: NOT(A OR B) = NOT(A) AND NOT(B). Verification by truth table across the 4 possible combinations of A and B — useful for transforming an OR+NOT circuit into a NAND-only circuit.

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EXERCISE 1 · TRUTH TABLES AND SIMPLIFICATION · 6H

Equipment: provided exercise sheet (5 logic functions with 2-3 variables), graph paper for Karnaugh maps.

(1h30) Building complete truth tables for 5 given logic functions (combinations of AND, OR, NOT provided in the brief).

(2h) Simplifying 3 of these functions using Boolean algebra (applying the laws covered in class, including De Morgan).

(2h30) Simplifying all 5 functions using Karnaugh maps, comparing the results against those obtained with Boolean algebra.

SOLUTION — EXERCISE 1

Example function to simplify: F = A.B + A.NOT(B) + NOT(A).B

Via Boolean algebra: A.B + A.NOT(B) = A.(B+NOT(B)) = A.1 = A. So F = A + NOT(A).B. By distributivity: A + NOT(A).B = (A+NOT(A)).(A+B) = 1.(A+B) = A + B.

Via Karnaugh map (2 variables A, B): the 3 cells equal to 1 (AB=11, AB=10, AB=01) form a grouping that reads directly as A + B — an identical result, validating the method both ways.

Teaching point to emphasise: the Karnaugh map becomes notably faster than Boolean algebra as soon as the number of variables increases (3 or 4 variables) — this is why it is favoured in industrial practice.

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EXERCISE 2 · DESIGN — TRAFFIC LIGHT CONTROL · 8H

Brief: design the logic circuit for a simple 2-way intersection (lane A has priority during peak hours, lane B is secondary). An input variable H indicates whether it is peak hour (H=1) or not (H=0). A variable S indicates that a vehicle is detected on the secondary lane B (ground sensor). Output: lane A's light must be green (FA=1) except when it is not peak hour AND a vehicle is detected on B.

(1h) Formal definition of the input variables (H, S) and output (FA) from the brief.

(1h30) Building the complete truth table (4 combinations of H and S).

(2h) Simplifying the FA function using a Karnaugh map.

(1h30) Translating the simplified result into a logic diagram (AND/OR/NOT gates).

(2h) Physical build using 74XXX-series integrated circuits (74LS08 for AND, 74LS32 for OR, 74LS04 for NOT), testing with input switches and an output LED.

SOLUTION — EXERCISE 2

Truth table: H=0,S=0 → FA=1 (not peak hour, no vehicle on B, A stays green by default); H=0,S=1 → FA=0 (not peak hour BUT a vehicle is detected on B, so we yield); H=1,S=0 → FA=1; H=1,S=1 → FA=1 (absolute priority to A during peak hour, even with a vehicle on B).

Simplified function: FA = H + NOT(S), which literally reads as "light A is green if it is peak hour, or if no vehicle is detected on B".

Logic diagram: an OR gate with H as a direct input and NOT(S) (so a NOT inverter upstream on signal S), output FA.

Physical build: 1 inverter (74LS04) to generate NOT(S), 1 OR gate (74LS32) to combine H and NOT(S). Simple wiring using 2 integrated circuits, validated by testing all 4 switch combinations and observing the output LED.

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EXERCISE 3 · ELECTRONIC TESTING AND VALIDATION · 9H

Equipment: circuit built in Exercise 2, multimeter (acquired in Week 1), LED protection resistors (220Ω), regulated 5V power supply, breadboard.

(2h) Wiring check before power-up: trace continuity, absence of short circuits, component polarity.

(2h) Gradual power-up and measurement of the actual supply voltage on each integrated circuit.

(2h) Systematic testing of all 4 input combinations (H, S) and recording the output state (FA) each time, compared against the theoretical truth table from Exercise 2.

(2h) Diagnosing and fixing any malfunctions (wrong connection, faulty IC, logic error) using the multimeter.

(1h) Final presentation of the working circuit by each pair, with an oral explanation of the full reasoning (brief → truth table → simplification → diagram → build).

SOLUTION — EXERCISE 3

Expected validation grid: the 4 tested combinations must give exactly the results from the Exercise 2 truth table (FA=1,0,1,1 for H,S = 00,01,10,11). Any discrepancy should be explained by a wiring or component fault, never by a logic error if the Exercise 2 simplification was correctly validated.

Most common faults to anticipate: a reversed power pin on the integrated circuit (Vcc/GND), a missing or miscalibrated LED protection resistor, a poor breadboard contact.

◆ SUMMARY SHEET — WEEK 3 SELF-ASSESSMENT

1. I know the truth tables of AND, OR, NOT, NAND, NOR, XOR.

2. I can simplify a logic function using Boolean algebra, including De Morgan's laws.

3. I can build and read a Karnaugh map for 2, 3 or 4 variables.

4. I can translate a brief into input/output variables and a truth table.

5. I can translate a simplified function into a logic diagram using gates.

6. I can build a simple logic circuit using 74XXX-series integrated circuits.

7. I can test and validate a logic circuit using a multimeter.

8. I can diagnose a simple fault on a logic build.